1. Field of the Invention
The present invention relates to a pulse signal generation circuit which outputs a pulse signal generated by dividing a clock pulse signal and to a pulse signal generation method of outputting such a pulse signal.
2. Description of the Prior Art
Such a type of conventional pulse signal generation circuit has been disclosed in Japanese Laid-open Patent Application No. 64-12617, which is incorporated herein by reference.
The above pulse generation circuit is, as shown in FIG. 16, comprises a counter C for setting a frequency value, a memory M for storing data among which the data corresponding to the frequency value is read by using the frequency value as address signals, a first flip-flop F.sub.1 for latching and outputting data read from the memory, a full adder A for inputting the output of the first flip-flop F.sub.1, and a second flip-flop F.sub.2 for latching an added value of the full adder A by a predetermined clock signal.
The above pulse generation circuit adds the output of the first flip-flop F.sub.1 and the output of the second flip-flop F.sub.2, enters to the counter C a carry signal which is generated by the second flip-flop F.sub.2 when the added value latched by the second flip-flop F.sub.2 exceeds a predetermined value, and outputs the carry signal as a pulse signal of a frequency whose value is set in the counter C until the counter C prohibits the passing of the carry signal.
In the above-mentioned conventional pulse signal generation circuit, it is possible to output a pulse signal of the frequency whose value is set in the counter C and can be other than a power of 2.
However, this circuit has problems that it is necessary to read data corresponding to the frequency value from the memory M by using the frequency values as address signals so that the first flip-flop F.sub.1 may latch the data. Consequently, the number of processes is increased and the internal structure is complicated, which makes the production of the circuit time-consuming and also brings a disadvantage in terms of operational speed.